| RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study |
| Paper ID : 1139-IUGRC6 |
| Authors |
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Mohammed Mahmoud Eldesouky * University of Science and technology at Zewail City |
| Abstract |
| RISC-V is an open Instruction Set Architecture (ISA) that is expected to dominate the market in the next few years. It is forecasted that market will consume 62.4 billion RISC-V CPU cores by 2025. RISC-V is an open ISA that was introduced in 2010. In the past years it was commercialized and it is expected to dominate the market because it is efficient and open with numerous variants that serves almost every application from Internet of Things (IoT) to High Performance Computing (HPC). In this paper a RISC-V core is physically implemented as an ASIC using Nangate Open Cell Library 45nm PDK and its performance is compared to a 45nm based Spartan 6 FPGA implementation to assess the performance gap between FPGA and ASICs. The performance gap agrees with the reported in literature as ASIC implementations tend to have much higher frequencies and lower power and area however FPGA implementation has a very short development process and can be edited post implementation. |
| Keywords |
| FPGA ASIC RISC-V |
| Status: Accepted |